Vlsi lab manual using microwind

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Design and Implementation of ring oscillator Equipment Required: 1. Made the interconnections as per the circuit diagram using add a line option 4. The step by step procedure as follows Microwind 3. Report DMCA. Home current Explore. Words: 1, Pages: List of Experiments: 1. Design and implementation of an inverter 2.

Design and implementation of universal gates 3. Design and implementation of full adder 4. Design and implementation of full subtractor 5. Design and implementation of RS-latch 6. Include the screenshots of both the functional and block level RTL Diagrams.

Simulation Results of your Design. Your screenshot must include the complete input and output waveforms. Make sure you do NOT name your gate modules by the standard Gate names. Use names like e. Verify the working of this Full Adder made from your own logic gates. Verilog HDL codes of test-bench modules made for simulating the complete truth table of the respective Gates. Use these descriptions to: a. Simulate it and view its working. Generate the Verilog code file of your Inverter design.

A file selecting window will appear. A settings window will appear. Each main heading must contain the following by making a separate subheading for each: 1. Draw the Stick-Layout Diagram of an Inverter on your notebook. Select 0. Measure the length and width of your layout d. The tasks given in the lab include,. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters.

As covered in the lectures we know that the mobility of the holes is less than that of electrons, and in CMOS inverter pFET is responsible for the conduction of current leading a logic 1 at the output, while nFET is responsible for the conduction of current leading a logic 0 at the output. This means that the gate delay form low to high will be greater than the gate delay for low to high voltage.

Waqar Ahmad. Open DSCH and select the foundry cmos Save the design as Save as as Lab Save the design frequently during lab session. Draw the circuit diagram of inverter. Check for floating point if any. Simulate the Design 6. Make a Verilog file of the design. Open Microwind and select the foundry cmos Compile the Verilog file of inverter Lab Save the design.

Simulate the design using the Run command Analyze configuration delay, gate delay, current, power, and midpoint voltage. Repeat the design for different value of transistor size and supply voltage and carefully observe the changes in configuration delay, gate delay, current, power, and midpoint voltage. Manual Layout of Inverter 1.

Save the design as Save as as Lab02, and save the design frequently during the Lab session. Connect the two transistors using Metal 1 as per design. Draw the rails of V DD and ground rails above and below. Connect the nWell to V DD 8. Check the design using DRC for any design rule violation and correct the design in case of error, again run the DRC and check for errors. Or run the DRC after each change in the layout.

Check for Electrical connections to be valid. Add inputs and outputs to the design; also add virtual capacitance at the output in your design. Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area. Repeat the design using for different values of transistors dimensions, supply voltages. And observe the changes in configuration delay, gate delay, power, current, VTC, and area carefully. Make a conclusion of your observations.

Include the results in timing waveform format in your report Only follow the provided cover page format Simulation Analysis Include in your Lab Report. Task 2: Generate the automated layout of the CMOS inverter from schematic diagram and analyze its functionality,. As per discussion and design on white board in the Lab, this complex gate can be implemented as under. Observe the. Observe the values. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters Tool used: Microwind Lab Description:.

Observe the values of configuration. Lab Objective: In this lab students will design and implement the layouts of Multiplexer, Demultiplexer and Shifter. The tasks given in lab include:.